1. Field of the Invention
The present invention relates to a semiconductor device with conductivity modulation, such as an insulated gate bipolar transistor, and a method of manufacturing the same.
2. Description of the Background Art
FIG. 1 is a sectional view showing the structure of a conventional vertical insulated gate bipolar transistor (IGBT) disclosed in IEDM Transactions 1984, pp. 274-277.
Referring to FIG. 1, a p.sup.+ -type collector layer 21 is formed by a p.sup.+ -type semiconductor substrate. An n.sup.- -type base layer 22 is formed on one major surface of the p.sup.+ -type collector layer 21. A p-type impurity is selectively diffused in a partial region of the surface of the n.sup.- -type base layer 22, to form a p-type well region 23. Further, an n-type impurity of high concentration is selectively diffused in a partial region of the surface of the p-type well region 23, to form an n.sup.+ -type emitter region 24. A gate insulation film 26 is formed on the surface of a channel portion 25 of the p-type well region 23 between the surfaces of the n.sup.- -type base layer 22 and the n.sup.+ -type emitter region 24. The gate insulation film 26 is also formed on the surface of the n.sup.- -type base layer 22 to be integrated with a gate insulation film of an adjacent IGBT cell. A gate electrode 27 of polysilicon, for example, is formed on the gate insulation film 26, while an emitter electrode 28 of metal such as aluminum is formed to be electrically connected to both of the p-type well region 23 and the n.sup.+ -type emitter region 24. A collector electrode 29 of metal is formed on the back surface of the p.sup.+ -type collector layer 21 in common with respect to all of the IGBT cells.
N-channel MOS structure is provided in the vicinity of the channel portion 25. Thus, when positive voltage is applied to the gate electrode 27, electrons flow from the n.sup.+ -type emitter region 24 to the n.sup.- -type base layer 22 through the channel portion 25. On the other hand, holes of minority carriers are injected from the p.sup.+ -type collector layer 21 into the n.sup.- -type base layer 22. A part of the holes dissipate through recombination with the aforementioned electrons, while the remaining ones flow in the p-type well region 23 as hole current. Thus, the IGBT basically operates in a bipolar manner, and conductivity is increased by an effect of conductivity modulation in the n.sup.- -type base layer 22, thereby lower ON-state voltage and larger current capacity can be implemented as compared with a general power MOS transistor.
In general, an IGBT is provided therein with a parasitic pnpn thyristor in structure, and hence a latch-up phenomenon of such a parasitic thyristor must be suppressed. Therefore, operation of a parasitic bipolar transistor, which is formed by the n.sup.+ -type emitter region 24, the p-type well region 23 and the n.sup.- -type base region 22, is generally suppressed.
In a method of suppressing the operation of such a parasitic bipolar transistor, the n.sup.+ -type emitter region 24 and the p-type well region 23 are short-circuited with each other, furthermore, impurity concentration of the p-type well region 23 is increased in order to let the holes, that is the minority carriers, gathering from the n.sup.- -type base region 22 to the p-type well region 23, flow through the p-type well region 23 without turning on the parastic bipolar transistor.
In this method, impurity concentration in forming the p-type well region 23 has been generally increased and deep diffusion has been performed at a high temperature for a long time, while impurity diffusion in high concentration has been repeated a plurality of times, as the case may be.
Increase in depth of the p-type well region 23 leads to improvement in peak inverse breakdown voltage of p-n junction formed by the p-type well region 23 and the base layer 22. Thus, deep formation of the p-type well region 23 is required also in view of improvement in breakdown voltage of the device. For example, depth of 15 to 20 .mu.m is required for the p-type well region 23 in a device of breakdown voltage of 1000 V.
In the method of increasing impurity concentration of the p-type well region 23, however, a defect such as thermal distortion is caused when heat treatment is performed at a high temperature for a long time. Further, concentration distribution of the impurity is inevitably reduced as depth is increased, since the p-type well region 23 is formed by diffusion from the surface of the n.sup.- -type base layer 22. Thus, vertical resistance in the p-type well region 23 cannot be sufficiently reduced in its bottom portion, leading to insufficient prevention of a latch-up phenomenon.
In another method of suppressing operation of the parasitic bipolar transistor, the ratio of the surface of the n.sup.+ -type emitter region 24 within the surface of the p-type well region 23 is reduced to increase the ratio of holes flowing in the p-type well region 23 without passing under the n.sup.+ -type emitter region 24, i.e., to provide a bypass region. In particular, there is such possibility that large voltage drop caused by flow of a large amount of carriers through the well region 23 Just below the n.sup.+ -emitter one 24 may bring the transistor into an ON state in the vicinity of an end portion of the n.sup.+ -emitter region 23 near the channel portion 25, even if resistance of the p-type well region 23 is small. The aforementioned method of providing the bypass region is effective to reduce such possibility. In this method, however, the area of the channel portion 25 is decreased, whereby current capacity is reduced.
Further, a problem other than the latch-up phenomenon resides in a junction field effect transistor (JFET) effect caused between an adjacent pair of p-type well regions 23. In an IGBT, current flowing through the channel part 25 in an ON state flows through the n.sup.- -type base layer 22 between the adjacent pair of p-type well regions 23. As a space between the adjacent pair of p-type well regions 23 becomes small, a depletion layer occupies more part of the n.sup.- -type base layer 22 between the p-type well regions 23 to obstruct the flow of the current, whereby emitter-collector resistance components of the IGBT are increased. This is the JFET effect. ON-state voltage of the IGBT is increased by such JFET effect.
In an IGBT of high breakdown voltage, particularly, the substrate (n.sup.- -type base region 22) of low impurity concentration, i.e., high specific resistance is used and the deep p-type well region 23 is formed, whereby the JFET effect is further facilitated. Hence the space between IGBT cells cannot be reduced. Thus, it is hard to increase current capacity by fining the cells to increase the cell density.